The present invention relates to a semiconductor integrated circuit device having a memory array and a recovery circuit block for recovering the memory array using recovery fuse data represented by recovery fuse elements after an error of the recovery fuse data is corrected.
Basically, the present invention relates to a semiconductor integrated circuit device having a dynamic random access memory (DRAM) and, in particular, to a synchronous dynamic random access memory (SDRAM).
Japanese Unexamined Patent Application Publication No. 60-201599 (hereinafter referred to as Patent Document 1), in particular, FIG. 3 of this publication discloses a semiconductor integrated circuit device including a memory circuit (fuse circuit) for storing four defective addresses, each having eight bits, a memory circuit (fuse circuit) for storing 5 redundancy bits, and an error correction code (ECC) circuit. In this semiconductor integrated circuit device, the four defective addresses and 5 redundancy bits are supplied to the ECC circuit, which carries out an error correction. The defective addresses indicate addresses of defective memory cells in the memory array and are used to recover the memory array.
Japanese Unexamined Patent Application Publication No. 2002-94368 (hereinafter referred to as Patent Document 2), in particular, FIG. 11 of this publication discloses a semiconductor integrated circuit device in which a plurality of random access memories (RAMS) share an error correction circuit including one group of fuse elements and a cyclic redundancy code.